U.S. Pat. No. 3,643,231 entitled "Monolithic Associative Memory Cell" granted Feb. 15, 1972 to F. H. Lohrey and S. K. Wiedmann, and of common assignee herewith. The Lohrey et al patent discloses an associative memory storage cell having two cross-connected transistors with the word line for the cell connected to the common emitters of the two transistors and having each of the bases of the two transistors connected to the base of an input/output transistor. The emitter of each of these input/output transistors is connected to a separate bit line and the collectors of the input/output transistors are connected together and to the associative sense amplifier. To associatively search the memory, one of the bit lines is lowered. This causes the input/output transistor connected to the lowered bit line to conduct and thereby give no-match signal to the associative sense amplifier if its base is connected to the base of the conducting one of the two cross-connected transistors and it causes that transistor to remain nonconductive and thereby give a match signal to the associative sense amplifier if it is connected to the base of the non-conducting one of the two cross-connected transistors.
U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann and of common assignee herewith. The Berger et al patent discloses a monolithic semiconductor circuit comprising a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semiconductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.
U.S. Pat. No. 3,815,106 entitled "Flip-Flop Memory Cell Arrangement" granted June 4, 1979 to S. K. Wiedmann, and of common assignee herewith. The Wiedmann patent discloses a memory cell arrangement which allows the powering of only two row cells at any one time. This results in lower power dissipation in the cells and also permits the driving circuits to operate at a much lower power level, thereby further reducing the power dissipation per chip.
U.S. Pat. No. 3,816,758 entitled "Digital Logic Circuit" granted June 11, 1974 to H. H. Berger and S. K. Wiedmann, and of common assignee herewith. The Berger et al patent discloses a digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, an input adapted to receive a digitial logic signal, an output, a current source, means connecting said first transistor emitter to said current source, means connecting said first transistor base to said second transistor emitter, means connecting said first transistor collector and said second transistor base to said input, and means connecting said second transistor collector to said output.
U.S. Pat. No. 3,886,531 entitled "Schottky Loaded Emitter Coupled Memory Cell For Random Access Memory" granted May 27, 1975 to J. L. McNeill. The McNeill patent discloses a memory cell for a random access memory, the cell including a bistable circuit having first and second cross-coupled transistors with plural emitters. One emitter of each of the first and second transistors is coupled in common. The collector loads for the first and second transistors are provided by respective Schottky diodes which enable the differential voltage in the memory cell to remain low and the cell to be unsaturated over an order of magnitude of current increase to provide for a higher ratio of cell read current to cell store current. Additionally, hard saturation of the memory cell which would otherwise increase the write time is eliminated by this construction.
U.S. Pat. No. 3,993,918 entitled "Integrated Circuits" granted Nov. 23, 1976 to A. W. Sinclair. The Sinclair patent discloses a master/slave bistable arrangement which operates on current levels rather than voltage levels and with a single input of clock pulses. There are different bias current levels which are advantageously supplied by multi-layer current injection structures in integrated form.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson. The Peterson patent discloses a memory cell which comprises a word line, a pair of bit lines, a pair of current sources each having a first side coupled to a corresponding one of the bit lines; and a bistable circuit means operatively coupled to the word line and to another side of each of the current sources, whereby the bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the other bit line.
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating A Semiconductor Memory System" granted May 16, 1978 to H. H. Berger et al., and of common assignee herewith. The Berger et al patent discloses a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases. This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits. This permits high speed, low operating current, large scale memory systems to be built.
IBM Technical Disclosure Bulletin publication entitled "MTL Storage Cell" by S. K. Wiedmann, Vol. 21, No. 1, June 1978, pages 231-2.
"Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfired K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, Oct. 1972, pages 340-6.
"Integrated Injection Logic: A New Approach to LSI" By Kees Hart and Arie Slob, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 346-51.
From U.S. Pat. No. 4,090,255 a method and a circuit arrangement for driving an integrated semiconductor storage are known, the storage cells of which consist of flip-flops with bipolar transistors and Schottky diodes as read/write coupling elements and the load elements of which are high-ohmic resistors or transistors connected in the form of current sources. The read/write cycles of the storage cells, which are performed in several phases, are selected by level changes on the word and bit lines. For increasing the read and write speed as well as for reducing the power dissipation, the bit lines are discharged via the conductive storage cell transistors. Discharging of the bit lines via these conductive storage cell transistors is effected to ground. During the read phase of the storage, the bit lines are only slightly recharged, so that the recharge current flowing through the storage cell is very low.
In the past few years, there have been many developments in the field of logic arrays and integrated semiconductor storage technology with bipolar transistors, which are referred to as MTL (Merged Transistor Logic) or I.sup.2 L (Integrated Injection Logic) in the specialized literature. In this connection, attention is drawn, for example, to the articles in the IEEE Journal of Solid State Circuits, Vol. SC/7, No. 5, October 1972, pp. 340 ff. and 346 ff. Corresponding proposals are also contained in U.S. Pat. No. 3,736,477 as well as U.S. Pat. No. 3,816,748.
These concepts with bipolar transistors have short switching times and are particularly suitable for extremely highly integrated storages and logic circuit groups.
Storages with storage cells of bipolar transistors having a structure resembling that of MTLs necessitate a recharging of bit data and/or control line capacitances for selecting a storage cell. For this purpose, the voltage swing of the bit lines approximately corresponds to the voltage swing of the selected word lines. As previously described in U.S. Pat. No. 4,090,255, the capacitive discharge currents are discharged to ground via the storage cells of the selected word line and via the word line driver. With a greater number of storage cells in a matrix this has the disadvantage that the area requirements of the driver switching circuits, the power dissipation for each driver, and the delay period occurring during the selection of the word line increase disproportionately, so that the advantages of the MTL structure employed would be eliminated.
To avoid this disadvantage, German Offenlegungsschrift No. 28 55 866 proposes a method of driving a semiconductor storage and a circuit arrangement. [German Offenlegungsschrift No. 28 55 866 corresponds to U.S. patent application Ser. No. 101,366, entitled "Method and Circuit Arrangement For Controlling An Integrated Semiconductor Memory" filed Dec. 7, 1979 by Klaus Heuber and Siegfried Kurt Wiedmann]. This method is characterized in that in due time prior to selection, a control arrangement known per se generates control signals for the storage matrix as a function of a selection signal. These control signals are simultaneously applied to a discharge circuit, common to all storage cells, and to switching transistors which are thus switched on. As a result, the discharge currents of the line capacitances on the bit data and control lines flow through the switching transistors, being jointly discharged via the discharge circuit. This circuit arrangement is characterized in that the bit lines within the storage matrix are connected to a discharge line which, in turn, is connected to a discharge circuit, and that for control purposes, the discharge circuit and all word and/or bit line switching transistors are connected via lines to a control logic controlled by the selection signal of the storage chip.
Although these discharge methods as well as the circuit arrangements for implementing them, in addition to preventing capacitive peak currents on the voltage supply lines and permitting a relatively high degree of integration, permit using the minimum voltage swing on the word line, these solutions have the following disadvantages:
The discharge operation and the selection operation of the bit lines must be performed consecutively. The rise in the sensing current from the sensing circuit after selection of the bit lines decisively determines the access time to the storage cell. The bit and word line switching transistors operating parallel to each other must be switched on at the end of the selection period, so that the access time to the storage chip is prolonged.
The number of components required in the peripheral circuits of such a storage are, however, very great. In addition, the read signal supplied depends on the direct current emanating from the read/write amplifier.